1. Field of the Invention
The present invention relates generally to memory devices and, more particularly, to a duty cycle distortion compensation scheme for the output data of a memory device, such as a double-data rate (DDR) dynamic random access memory (DRAM) device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system generally depends upon which features of the memory are best suited to perform the particular function. Memory manufacturers provide an array of innovative fast memory chips for various applications, including Dynamic Random Access Memories (DRAM), which are lower in cost but have slower data rates, and Static Random Access Memories (SRAM), which are more costly but offer higher data rates. Although both DRAMs and SRAMs are making significant gains in speed and bandwidth, even the fastest memory devices cannot match the speed requirements of most microprocessors. Regardless of the type of memory, the solution for providing adequate memory bandwidth depends on system architecture, the application requirements, and the processor, all of which help determine the best memory type for a given application. Limitations on speed include delays in the chip, the package, and the system. Thus, significant research and development has been devoted to finding faster ways to access memory and to reduce or hide latency associated with memory accesses.
Because microprocessor technology enables current microprocessors to operate faster than current memory devices, circuit techniques for increasing the speed of memory devices are often implemented. For example, one type of memory device, which can contribute to increased processing speeds in the computer system, is a Synchronous Dynamic Random Access Memory (SDRAM). An SDRAM differs from a standard DRAM in that the SDRAM includes input and output latches to hold information from and for the processor under control (i.e., synchronous with) the system clock. Because input information (i.e., addresses, data, and controls signals) is latched, the processor may safely perform other tasks while waiting for the SDRAM to finish its task, thereby reducing processor wait states. After a predetermined number of clock cycles during which the SDRAM is processing the processor's request, the processor may return to the SDRAM and obtain the requested information from the output latches.
A technique for increasing the speed of an SDRAM is to implement a Double Data Rate (DDR) SDRAM. In a Double Data Rate (DDR) memory device, the data transfer rate is twice that of a regular memory device, because the DDR's input/output data can be strobed twice for every clock cycle. That is, data is sent on both the rising and falling edges of the clock signal rather than just the rising edge of the clock signal as in typical Single Data Rate (SDR) systems.
As data rates are increased to meet the demands of today's high-speed processing systems, distortion in the data output caused by the switching of components within the memory device may become more significant. Duty cycle distortion caused by the data output registers and latches of the data output of a DDR DRAM can be particularly problematic as data rates increase. Because data is read from the DDR DRAM on both the rising and falling edges of the clock signal, two data output windows (or “eyes”) during which valid data may be read at the output pin of the DRAM occur for each cycle of the clock. If the data output latch distorts the duty cycle of the output data, the size of the windows during which data is valid may be significantly reduced, thus potentially leading to loss of data or reading of incorrect data as data rates increase.
Such duty cycle distortion may result from differences in processing parameters and other processing variations which occur with respect to the different types of components in the output latches and drivers. Additional factors, such as ambient temperature and voltage variations also contribute to duty cycle distortion. As a result, differences in slew rates between p-and n-channel output devices, differences in the mobility of holes in p-channel devices and the mobility of electrons in n-channel devices, variations in voltage levels applied to the various devices, and so forth, all can contribute to significant data duty cycle distortion. Processing variations may be compensated by post-production tuning to adjust for the differences between the p-and n-channel devices. Such a solution, however, is time-consuming and must be performed separately for each memory device, and cannot compensate for differences, such as ambient temperature and voltage variations, that may occur during actual operation of the device.
Thus, it would be desirable to provide a memory device having a circuit which actively compensates for output data duty-cycle distortion during operation of the memory device. Such a circuit could eliminate or reduce post-production tuning, while potentially more accurately responding to and compensating for the duty-cycle distortion caused by the output latch of the memory device.
The present invention thus may address one or more of the problems set forth above.